In virtually all communication systems, data is transferred from a transmitting node of the communication system to a receiving node over a communication path. Such a path may be a wired or wireless connection between the communicating nodes. In many of these systems, the data take the form of a digital signal transferred at a substantially constant rate over the connection. Normally, the data signal presents a series of binary digits (“bits”) that represent the digital information being transmitted to form a serial communication path. Further, several such series of bits transferred simultaneously may form a multi-channel, parallel communication connection.
Some communication systems also supply a data clock signal over the same connection to provide timing information for the data signal. Typically, the data signal is sampled, or “clocked,” at each logic “low” to logic “high” transition of the data clock to identify each bit being transferred. However, other communication systems do not provide a clock signal along with the data signal over the connection, instead relying on the receiving node's knowledge of the transfer rate of the data signal to allow proper interpretation of the data signal.
Unfortunately, without a clock signal supplied by the transmitting node, drift of the data signal frequency, variations in the frequency of a local oscillator from which the data clock is derived, and similar problems may cause the receiving node to improperly clock the data signal. To counteract such problems, the receiving node is often equipped with a data clock recovery system to help ensure proper sampling of the data signal.
Typically, an important portion of such a data clock recovery system may be termed a phase generator, which is employed to continually adjust the phase of a locally-generated clock signal to properly align with the data signal for clocking purposes.
One example of a phase generator 1 is illustrated in FIG. 1. Generally, the phase generator 1 accepts as input a reference clock RCLK, a phase shift “up” signal PUP, and a phase shift “down” signal PDOWN. As is described in greater detail below, the reference clock RCLK is utilized to generate a higher-frequency data clock OUTCLK having two phases, OUTCLKP and OUTCLKN, separated in phase by 180 degrees. The phase of the sampling clock OUTCLK is adjusted according to the phase shift signals PUP and PDOWN. Typically, each pulse of the PUP signal causes the phase of the sampling clock OUTCLK to be advanced “up” some portion of a period, while a pulse of the PDOWN signal causes the phase of the sampling clock OUTCLK to be delayed “down” a similar amount. Typically, the PUP and PDOWN signals are generated by another portion of the data clock recovery system, often based upon a phase detector or similar device configured to determine the relative phase of the data signal and the data clock.
As seen in FIG. 1, the phase generator 1 includes a phase-locked loop (PLL) 20, a multiplexer 40, a phase interpolator 60, a thermometer code register 80, and a counter 90. The PLL 20 uses the reference clock RCLK to generate a multiphase clock to be provided to the multiplexer 40. In the particular example of FIG. 1, the PLL 20 generates eight equally-spaced phases P0 through P7, each of which is separated in phase from adjacent phases by 45 degrees. A timing diagram of the phases P0-P7 is shown in FIG. 2. Other PLLs may generate more or fewer clock phases, depending on the requirements of the particular application. Typically, 4, 8, or 16 clock phases are produced. In other examples of the phase generator 1, a delay-locked loop (DLL) may be employed in lieu of the PLL 20.
FIG. 3 provides a more detailed view of the PLL 20. The reference clock RCLK is received by a phase detector 21, which compares the phase of the reference clock RCLK with a low-frequency clock 28 described more fully below. As a result of this comparison, a phase advance signal 24 and a phase delay signal 25 are generated. The phase advance signal 24 indicates when the low-frequency clock 28 is required to be advanced in order to maintain its phase relationship with the reference clock RCLK. Conversely, the phase delay signal 25 becomes active when the phase detector 21 determines that the low-frequency clock 28 must be delayed to maintain its phase relationship with the reference clock RCLK.
A charge pump 22 receives and processes the phase advance signal 24 and the phase delay signal 25 to generate a control voltage signal 26 across a capacitor C. The capacitor C acts as a storage medium for the charge pump 22, thus exhibiting a voltage indicating whether the frequency of the low-frequency clock 28 should be increased or decreased to alter its phase relative to the reference clock RCLK. Additionally, the capacitor C often acts as a low-pass filter to affect how quickly the PLL 20 reacts to changes in the reference clock RCLK.
The control voltage signal 26 is received by a voltage-controlled oscillator (VCO) 30, which generates a high-frequency clock 27 whose frequency is determined by the voltage level of the control voltage signal 26. More specifically, the higher the voltage level of the control voltage signal 26, the higher the frequency of the high-frequency clock 27, and vice-versa. The frequency of the high-frequency clock 27 is then divided by a 1/N divider 23, where N is typically a power of 2, such as 16. In that case, a 100 megahertz (MHz) reference clock RCLK would be phase-locked with a 100 MHz low-frequency clock 28, which is turned is derived from a 16*100 MHz=1.6 gigahertz (GHz) high-frequency clock 27 generated by the VCO 30. Other values of N may be employed in the alternative.
In the PLL 20 of FIG. 3, the high-frequency clock 27 generated by the VCO 30 is actually one of the multiphase clock phases P0-P7, all of which are generated by the VCO 30. The PLL 20 thus serves primarily as a multiphase clock generator, which allows generation of a high-frequency multiphase clock from a single-phase, relatively low-frequency, reference clock RCLK. FIG. 4 depicts a particular example of the VCO 30 in greater detail. Four delay elements 32, labeled 32a-32d, form a ring oscillator used to generate the high-frequency clock 27 having a frequency controlled by the control voltage signal 26. More specifically, each delay element 32 receives an input biphase signal by way of a positive input INP and a negative input INN, and produces an output biphase signal composed of a positive output OUTP and a negative output OUTN. Each positive output OUTP of a particular delay element 32 thus produces a signal 180 degrees out of phase with its corresponding negative output OUTN. Given the arrangement of FIG. 4, each delay element 32 produces two of the eight phases P0-P7 of the multiphase clock shown in FIG. 2, wherein the two phases are out of phase by 180 degrees. For example, phases P0 and P4 may be produced by the first delay element 32a, phases P1 and P5 may be generated by the second delay element 32b, and so on.
The total time delay of a roundtrip about the oscillator ring is essentially equivalent to one-half the period of the high-frequency clock 27 and each of the clock phases P0-P7. This roundtrip delay is controlled, in turn, by the delay exhibited by each delay element 32. The delay of each delay element 32 is controlled in turn by the control voltage signal 26, which is processed by a bias voltage controller 31 to produce a positive bias control signal 34 and a negative bias control signal 36.
One particular example of a delay element 32 is provided in the simplified schematic diagram of FIG. 5. The gate of an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) QINP is driven by the positive input INP of the delay element 32. As INP rises in voltage, QINP tends to conduct current, causing its drain terminal, connected to the negative output OUTN, to drop in voltage. Conversely, when the voltage level of INP falls, OUTN rises. A second MOSFET QINN, whose gate is coupled with the negative input INN and whose drain is coupled with the positive output OUTP, operates in a similar fashion.
The propagation delay between the inputs INP, INN and the outputs OUTP, OUTN is determined in part by the negative bias control signal 36 from the bias voltage controller 31. The negative bias control signal 36 drives a MOSFET QN to alter a bias current flowing through either of the input MOSFETS QINP, QINN. As the negative bias control signal 36 increases, the bias current tends to increase as well, and vice-versa.
Changing the bias current in such a fashion tends to alter the magnitude of the voltage swings experienced by the outputs OUTP, OUTN. To compensate for the change in bias current to maintain a relatively constant amplitude for the outputs OUTP, OUTN, the positive bias control signal 34 from the bias voltage controller 31 is utilized. The positive bias control signal 34 drives the gates of four p-channel MOSFETs QBP1-QBP4, configured as two active resistive loads, each of which is coupled with one of the outputs OUTP, OUTN and a drain voltage VDD. Each of the loads is driven by the positive bias control signal 34 to alter the amount of resistive load imparted by QBP1-QBP4 upon the outputs OUTP, OUTN, thus generally controlling the delay exhibited by the delay element 32.
To maintain a substantially constant voltage amplitude for the outputs OUTP, OUTN, an increase in bias current due to an increase in the negative bias control signal 36 is typically matched with a commensurate voltage drop in the positive bias control signal 34. Such a drop in voltage reduces the resistive load imparted by QBP1-QBP4, which in turn reduces the time delay in voltage transitions at the outputs OUTP, OUTN due to a lower R-C time constant produced by the active resistive load and a load capacitance (not shown) at each of the outputs OUTP, OUTN. Reducing the time delay exhibited by each delay element 32 in such a manner results in an increase in the frequency of the clock phases P0-P7 and the high-frequency clock 27 generated by the VCO 30. Conversely, decreasing the bias current and increasing the active load of each of the delay elements 32 results in a reduction of the frequency of the clock phases P0-P7 and the high-frequency clock 27. Thus, the frequency of the clock phases P0-P7, which are typically set to match the expected data rate of a data signal being received, are primarily determined by the positive and negative bias control signals 34, 36 from the bias voltage controller 31.
FIG. 6 illustrates one particular simplified example of the bias voltage controller 31. In this case, two MOSFETS QA and QB are employed to generate the positive bias control signal 34 from the control voltage signal 26 of the charge pump 22 of the PLL 20. As the control voltage signal 26, which drives the gate of QA, increases, the level of electrical current through both QA and QB increases, thus lowering the voltage at the gate of QB, and hence the positive bias control signal 34. In the bias voltage controller of FIG. 6, the control voltage signal 26 is passed through as the negative bias control signal 36. Thus, as the negative bias control signal 36 increases, the positive bias control signal 34 decreases, and vice-versa, in accordance with the requirements of the delay element 32 discussed above, so that increases in the control voltage signal 26 result in increases in frequency of the clock phases P0-P7. Conversely, as the voltage level of the control voltage signal 26 decreases, so does the frequency of the clock phases P0-P7. Other circuits and methods not described herein have also been employed in other implementations of the bias voltage controller 31.
In one specific example of the bias voltage controller 31 and each delay element 32, the widths or sizes of the various FETs involved in generating the positive and negative bias control signals 34, 36 are controlled. More specifically, the ratio of the widths of QN to QA is essentially equal to the ratio of the widths of (QBP1+QBP2) (or QBP3+QBP4) to QB. Further, the widths of QBP1 and QBP2 are essentially equal, as are QBP3 and QBP4. Controlling the width ratios of the various FETs in such a manner helps ensure that the voltage levels of the positive and negative bias control signals 34, 36 relate to expected bias current levels and active resistive load values relative to the control voltage signal 26 for proper control of the frequency of the clock phases P0-P7.
Returning to FIG. 1, four clock phases, labeled CLKAP, CLKAN, CLKBP and CLKBN, are selected from the eight clock phases P0-P7 from the PLL 20 by way of the multiplexer 40 for ultimate delivery to the phase interpolator 60. Two of the four selected phases, CLKAP and CLKBP, are adjacent phases between which the desired output clock OUTCLK, as defined by the two output phases OUTCLKP and OUTCLKN, is situated. The third and fourth selected phases CLKAN and CLKBN are the negative phases of the first two phases, CLKAP and CLKBP. For example, in reference to FIG. 2, if P1 is selected as CLKAP, then CLKBP is P2, CLKAN is P5, and CLKBN is P6.
The selection of the four phases CLKAP, CLKAN, CLKBP and CLKBN is performed in FIG. 1 by way of a three-bit phase selection value PSEL(2:0) generated by the three-bit counter 90. The phase selection value PSEL(2:0) is incremented by a COUNTUP signal and decremented by a COUNTDOWN signal from the thermometer code register 80, which in turn is driven by the phase up and down signals, PUP and PDOWN, referenced above. The thermometer code register 80 produces a 32-bit thermometer code TC(31:0) employed by the phase interpolator 60 to generate the desired phase for the output clock OUTCLK between CLKAP and CLKBP. Other sizes for the thermometer code register 80, such as 16 bits, may be seen in other examples. If the desired phase advances out of the range between CLKAP and CLKBP, the thermometer code register 80 issues an indication on the COUNTDOWN signal to decrement the phase selection value PSEL. For example, if CLKAP is P1, a pulse or similar indication on the COUNTDOWN signal will shift CLKAP to P2, and the other three of the four selected phases CLKBP, CLKAN, CLKBN will be shifted accordingly. On the other hand, a COUNTUP pulse will shift CLKAP from P1 to P0, and the other phases CLKBP, CLKAN and CLKBN will be changed correspondingly.
FIG. 7 provides a simplified schematic diagram of the phase interpolator 60. Generally, each bit ‘X’ of the thermometer code TC(31:0) from the thermometer code register 80 drives a pair of n-channel MOSFETs QSX, QBX configured to sink current when the corresponding thermometer code bit is active. For example, when thermometer code bit TC31 is active, the voltage at the gate terminal of QS31 is elevated, causing both QS31 and QB31 to conduct current through either of a pair of MOSFETs QAP or QAN, depending on the state of the CLKAP and CLKAN signals. The MOSFETs QS31-QS0, QB31-QB0 thus collectively provide a current weighting circuit, wherein the MOSFETs QS31-QS16, QB31-QB16 associated with the most significant half of the thermometer code TC(31:16) provide current for QAP and QAN associated with CLKAP and CLKAN. Similarly, QS15-QS0 and QB15-QB0 identified with the least significant half of the thermometer code TC(15:0) provide current for the transistors QBP and QBN driven by CLKBP and CLKBN, respectively.
As shown by way of the timing diagram of FIG. 8, the current weighting circuit QS31-QS0, QB31-QB0, as driven by the thermometer code TC(31:0), determines the phase of the output clock phases OUTCLKP, OUTCLKN relative to CLKAP, CLKAN, CLKBP and CLKBN. Typically, a contiguous 16 bits of the thermometer code TC(31:0) are set to logic one, while the remainder are set to zero so that the total amount of current drawn through QAP, QAN, QBP and QBN remains substantially constant. The distribution of ones in the thermometer code TC(31:0) among its most and least significant halves determines the relative phase of the output clock phases OUTCLKP, OUTCLKN between CLKAP, CLKAN and CLKBP, CLKBN. More specifically, the more ones that reside within the most significant portion of the thermometer code TC(31:16), the closer the transitions of the output clock phases OUTCLKP, OUTCLKN are to those of CLKAP and CLKAN. Conversely, the more ones that reside within the least significant half of the thermometer code TC(15:0), the closer the transitions of the output clock phases OUTCLKP, OUTCLKN reside to the transitions of CLKBP and CLKBN. For example, as shown graphically in FIG. 8, a thermometer code TC(31:0) value (in hexadecimal notation) of 7FFF8000H (in binary notation, 01111111111111111000000000000000B) results in transitions of the positive output clock phase OUTCLKP being positioned approximately 1/16 of the time delay between CLKAP and CLKBP after CLKAP. Similarly, a thermometer code TC(31:0) value of 0001FFFEH (00000000000000011111111111111110B) results in the positive output clock phase OUTCLKP transitions occurring 1/16 of the time delay between CLKAP and CLKBP before CLKBP. FIG. 8 shows other relationships between the location of the positive output clock phase OUTCLKP and the thermometer code TC(31:0). The negative output clock phase OUTCLKN makes its voltage transitions substantially at the same time as the positive output clock phase OUTCLKP.
Typically, for proper operation of the phase interpolator 60 of FIG. 7, the interpolator bias current and loading bandwidth should be set appropriately for the particular frequency range of the output clock OUTCLK. For example, the loading bandwidth and the bias current should be matched with the output clock OUTCLK frequency so that full voltage swing of the output clock OUTCLK is allowed, while preventing any unwanted ringing of the output clock OUTCLK signal. As shown in the particular example of FIG. 7, the bias current is set by way of an interpolator bias voltage 62 coupled to the source terminal of each of the selection MOSFETs QS31-QS0 of the current weighting circuit of the interpolator 60. The loading bandwidth of the interpolator 60 is related to the R-C time constant associated with a resistance R, coupled between each of the output phases OUTCLKP, OUTCLKN and a drain voltage VDD, and a load capacitance CL associated with each of the output phases OUTCLKP, OUTCLKN. The load capacitance CL is normally of function of the layout and components of the circuitry driven by the output clock phases OUTCLKP, OUTCLKN. The resistance R is normally derived from either a fixed passive component or a fixed active transistor loading circuit.
Typically, the resistance R and the load capacitance CL are fixed for a particular interpolator 60 design, thus enforcing a fixed interpolator 60 loading bandwidth. Control of the bias current is similarly limited in most cases. However, more communications systems employing a phase generator are desired to operate with a wide range of input data stream frequencies, thus making a fixed loading bandwidth and/or bias current for the interpolator less than desirable.